As integrated circuits (IC's) have become more complex with larger numbers of components (e.g. transistors, capacitors, etc.), techniques for testing and debugging the circuitry on the IC chips have also become more complex. Original testing techniques usually involved applying stimulus signals to the input pins of the IC and monitoring the output results and also reading internal registers of the IC. Due to the complexity of current IC's, however, it is no longer sufficient merely to supply a series of test signals at the input pins of the IC chip under test and see what happens on the output pins and to read the registers. Instead, it has become necessary to tap various internal signals at various internal test points of the IC chip that would otherwise be hidden from the outputs, so that a more detailed view of the internal workings of the many components or sub-circuits of the IC chip may be obtained. The internal signals are, thus, routed to test pads, where the signals can be measured by probes touching the test pads. Ordinarily, several such test pads and probes are used for one IC chip. As the IC chips have become more complex with larger numbers of components, however, it has become impractical to simultaneously probe each test point, since there may be several hundred or thousands of desired test points. There is physically not enough room to apply a test probe to a test pad for each test point or internal signal. Therefore, it has become necessary to multiplex the internal signals together to select only a subset of the internal signals to be sent to a reasonable number of the test pads at one time. The tests are typically repeated with different subsets of the internal signals selected each time in order to sample all of the desired test points and internal signals.
All of the internal signals from all test points 100 are, thus, routed to a multiplexer 102, as shown for an exemplary IC 104 in FIG. 1. Each of the dots in FIG. 1 represents a test point 100 from which signal traces, wires or conductive paths 106 carry the internal signals to the multiplexer 102. The test points 100 are typically arranged in hierarchical levels 108, 110 and 112 that correspond to levels of “functional blocks” or “functional units” of the IC 104. At the lowest level 108 (level 3), the test points 100 typically involve groups 114 of related test points 100, such as for a particular small portion of the overall IC 104. The lowest levels 108 (levels 3), which are typically “component blocks” of the IC 104, may include one or more of the groups 114 of related test points 100. The next level 110 (level 2) may include one or more of the previous levels 108 (levels 3), and so on. At each succeeding level 108, 110 and 112, the signal traces 106 are typically aggregated into ever larger groups, so that by the time the signal traces 106 reach the multiplexer 102, there may be several hundred or thousands of the signal traces 106. Under control of test equipment (not shown), the multiplexer 102 typically selects one of the groups 114 of the signal traces 106 to supply selected internal signals to test pads 116.
With several hundred or thousands of the signal traces 106 to be routed around the IC 104 from the test points 100 to the multiplexer 102, chip layout becomes more costly, difficult and time-consuming. The signal traces 106 take up considerable space on the IC 104, which already contains many components for performing the actual functions of the IC 104. Determining the most efficient, economical and unobtrusive layout for the signal traces 106 to avoid interfering with the spaces for the components of the IC 104 requires significant time and resources.
It is with respect to these and other background considerations that the subject matter herein has evolved.